1. Field of the Invention
This invention is related to the field of integrated circuits and, more particularly, to detecting jitter in integrated circuits.
2. Description of the Related Art
Digital logic generally relies on a clock or clocks to launch inputs and sample outputs to be launched on a subsequent clock cycle. Ideally, each cycle of the clock signal is identical to the other cycles. Particularly, the rising and falling edges of the clock signal occur at the same point in time in each clock cycle in an ideal clock signal.
Unfortunately, real integrated circuits do not have ideal clock signals. Instead, there is a certain amount of variation in the clock signal from clock cycle to clock cycle (e.g. the rising and falling edges may occur at different times). The variation may have a number of sources, and is generally referred to as jitter. For example, the circuitry that generates the clock signal (e.g. a phase locked loop (PLL)) may be a source of jitter. Additionally, effects that occur during the clock distribution (such as variation in the power supply voltage, interference from nearby signals or background noise, etc.) may be a source of jitter.
Digital logic designers may design for a certain amount of jitter in a given integrated circuit design, based on analysis of the clock generation circuitry, characteristics of the semiconductor fabrication process that will be used to manufacture the integrated circuit, the clock distribution network, the size of the integrated circuit, etc. However, the actual jitter experienced in the integrated circuit is often unknown. The actual integrated circuit may be experiencing less jitter than expected (in which case a higher operating frequency may be possible for the integrated circuit) or more jitter than expected (and the additional jitter may be a source of problems being experienced with the integrated circuit).